Space assets and technology for bushfire management

The financial, emotional, and ecological impacts of bushfires can be devastating. This report was prepared by the participants of the Southern Hemisphere Space Studies Program 2021 in response to the topic: “How space assets and technologies can be applied to better predict and mitigate bushfires and their impacts.” To effectively reach the diverse set of stakeholders impacted by bushfires, Communication was identified as a key enabler central to any examination of the topic. The three pillars “predict”, “mitigate” and “communicate” were identified to frame the task at hand. Combining the diverse skills and experience of the class participants with the interdisciplinary knowledge gained from the seminars, distinguished lectures, and workshops during the SHSSP21 program, conducted a literature review With specific reference to the 2019-20 Australian fire season, we looked at the current state of the art, key challenges, and how bushfires can be better predicted and mitigated in the future. Comparing this to the future desired state, we identified gaps for each of the three domains, and worked across teams to reach consensus on a list of recommendations. Several of these recommendations were derived independently by two or more of the three groups, highlighting the importance of a holistic and collaborative approach. The report details a number of recommendations arising from this Where applicable, we also aligned our discussion with the experience and lessons from other countries and agencies to consider,learn from and respond to the international context, as others develop systems using space technology to tackle similar wildfire issues

Study of a Phase Locked Loop based Clock and Data Recovery circuit for 2.5 Gbps data-rate

Phase Locked Loop (PLL)-based Clock and Data Recovery (CDR) circuits play a big role in communication systems for High-Energy Physics (HEP) since are used to generate a high-quality clock signal that maintains synchronicity between the electronic systems. The CDR topology proposed in this thesis can be used to support the development of ASIC that finds application in high-speed link communication systems in the clock distribution system of the High Luminosity Large Hadron Collider (HL-LHC) detectors at CERN. The thesis results from a study based on a theoretical analysis supported by simulations. This proposed work aims to describe the operation of a PLL-based CDR through a highlevel behavioural analysis in Verilog. Advanced analyses are performed by using the Cadence Simulation Platform for modelling the system and Python scripting for requirement definition and post-processing of the data. The dependency of the phase noise and jitter of the PLL is a topic that is relevant in systems designed for high-frequency synthesis, and the analysis of the jitter behaviour is required to minimize the noise contribution. During the design phase, each architectural choice comes with pros and cons, therefore high-level considerations are derived from this study. Different sources of noise are introduced and the effects on the CDR operation are studied to minimize the jitter contribution coming from the reference data stream and from the Digital Control Oscillator (DCO). Furthermore, three CDR topologies that differ from the implementation logic of the downsampler connected at the output of the phase detector are compared. The comparison is done in terms of architectural complexity, bandwidth, jitter, and time to lock. As a result of the study, it is possible to conclude that a different implementation of downsampler logic generates a different phase detector gain in the feedback system, changing the dynamics of the system and its behaviour both in the time and frequency domains. However, it is possible to compensate for the variation of the phase detector gain by selecting different parameters for the digital filter, making in principle the behaviour of the three solutions equivalent

Study of a Phase Locked Loop based Clock and Data Recovery Circuit for 2.5 Gbps data-rate

Phase Locked Loop (PLL)-based Clock and Data Recovery (CDR) circuits play a big role in communication systems for High-Energy Physics (HEP) since are used to generate a high-quality clock signal that maintains synchronicity between the electronic systems. The CDR topology proposed in this thesis can be used to support the development of ASIC that finds application in high-speed link communication systems in the clock distribution system of the High Luminosity Large Hadron Collider (HL-LHC) detectors at CERN. The thesis results from a study based on a theoretical analysis supported by simulations. This proposed work aims to describe the operation of a PLL-based CDR through a highlevel behavioural analysis in Verilog. Advanced analyses are performed by using the Cadence Simulation Platform for modelling the system and Python scripting for requirement definition and post-processing of the data. The dependency of the phase noise and jitter of the PLL is a topic that is relevant in systems designed for high-frequency synthesis, and the analysis of the jitter behaviour is required to minimize the noise contribution. During the design phase, each architectural choice comes with pros and cons, therefore high-level considerations are derived from this study. Different sources of noise are introduced and the effects on the CDR operation are studied to minimize the jitter contribution coming from the reference data stream and from the Digital Control Oscillator (DCO). Furthermore, three CDR topologies that differ from the implementation logic of the downsampler connected at the output of the phase detector are compared. The comparison is done in terms of architectural complexity, bandwidth, jitter, and time to lock. As a result of the study, it is possible to conclude that a different implementation of downsampler logic generates a different phase detector gain in the feedback system, changing the dynamics of the system and its behaviour both in the time and frequency domains. However, it is possible to compensate for the variation of the phase detector gain by selecting different parameters for the digital filter, making in principle the behaviour of the three solutions equivalent. Keywords: PLL-based CDR, High-speed Link communication systems, low-noise PLL

Parallelizing TTree::Draw functionality with PROOF

In ROOT, the software context of this project, multi-threading is not currently an easy option, because ROOT is not by construction thread-aware and thread-safeness can only be achieved with heavy locking. Therefore, for a ROOT task, multi-processing is currently the most eective way to achieve cuncurrency. Multi-processing in ROOT is done via PROOF. PROOF is used to enable interactive analysis of large sets of ROOT les in parallel on clusters of computers or many-core machines. More generally PROOF can parallelize tasks that can be formulated as a set of independent sub-tasks. The PROOF technology is rather ecient to exploit all the CPU's provided by many-core processors. A dedicated version of PROOF, PROOF-Lite, provides an out-of-the-box solution to take full advantage of the additional cores available in today desktops or laptops. One of the items on the PROOF plan of work is to improve the inte- gration of PROOF-Lite for local processing of ROOT trees. In this project we investigate the case of the Draw functionality and its implementation via PROOF

Open-Loop Switched-Capacitor Integrator for Low Voltage Applications

An architecture of a switched-capacitor integrator that includes a charge buffer operating in an open-loop is hereby proposed. As for the switched-capacitor filters, the gain of the proposed integrator, which is given by the input/output capacitor ratio, ensures desensitization to process, voltage, and temperature variations. The proposed circuit is suitable for low voltage supplies. It enables a significant power saving compared to a traditional switched-capacitor integrator. This was demonstrated through an analytical comparison between the proposed integrator and a traditional switched-capacitor integrator. The mathematical results were supported and verified by simulations performed on a circuit prototype designed in 16 nm finFET technology with 0.95 V supply. The proposed switched-capacitor integrator consumes 76 µW, resulting in more than twice the efficiency for the traditional closed-loop switched-capacitor filter as an input voltage equal to 31.25 mV at 7 ns clock period is considered. The comparison of architectures was led among the proposed integrator and the state-of-the-art technology in terms of the figure of merit

SWEAT: Snow Water Equivalent with AlTimetry

International audienceTeam Orange would like to thank FFG and ESA for organising the Summer School Alpbach 2016. Also thanks to all the tutors and lecturers guiding Team Orange towards this product, and a special thank to our team tutors. Abstract Snow Water Equivalent (SWE) is not directly measured by current satellite missions but has a significant impact on society and our lack of understanding contributes to significant inaccuracies in current estimations of hydrological and climate models, calculations of the Earth's energy balance (albedo) and flood predictions. To address this, the SWEAT (Snow Water Equivalent with AlTimetry) mission aims to measure SWE directly on sea ice and land in the polar regions above 60 • and below-60 • latitude. The primary scientific objectives are to (a) improve estimations of global SWE from passive microwave products and (b) improve numerical snow and climate models. The mission will implement a novel combination of Ka-and Ku-band radioaltimeter technology, each providing different snow penetration properties. Airborne Laser altimeter campaigns will shadow the satellite orbit path early, middle and late winter for the first two years of the mission to confirm Ka-Band surface measurement accuracies. The combined difference in signal penetration results will enable more accurate determination of SWE.Therefore, the SWEAT mission aims to improve estimations of global SWE interpreted from passive microwave products, and improve the reliability of numerical snow and climate models